Analog
6.6 Analog
6.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
6.6.1.1 12-bit ADC operating conditions
Table 22. 12-bit ADC operating conditions
Typ.1
Symbol Description
Conditions
Absolute
Min.
1.71
-100
Max.
3.6
Unit
V
Notes
VDDA
Supply voltage
Supply voltage
—
ΔVDDA
Delta to VDD (VDD
-
0
+100
mV
2
2
VDDA
)
ΔVSSA
Ground voltage
Delta to VSS (VSS
-
-100
0
+100
mV
VSSA
)
VREFH
ADC reference
voltage high
1.13
VSSA
VREFL
VDDA
VDDA
V
V
VREFL
Reference
voltage low
VSSA
VSSA
VADIN
CADIN
Input voltage
—
4
VREFH
5
V
Input
capacitance
• 8/10/12 bit
modes
—
—
—
pF
RADIN
RAS
Input resistance
2
5
5
kΩ
kΩ
Analog source
resistance
12 bit modes
fADCK < 4MHz
3
—
—
fADCK
ADC conversion ≤ 12 bit modes
clock frequency
4
5
1.0
—
—
18.0
MHz
Ksps
Crate
ADC conversion ≤ 12 bit modes
rate
No ADC hardware
averaging
20.000
818.330
Continuous
conversions enabled,
subsequent conversion
time
1. Typical values assume VDDA = 3.0 V, Temp = 25°C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. The analog source resistance should be kept as low as possible in order to achieve the
best results. The results in this datasheet were derived from a system which has <8 Ω analog source resistance. The RAS
/
CAS time constant should be kept to <1ns.
4. To use the maximum ADC conversion clock frequency, the ADHSC bit should be set and the ADLPC bit should be clear.
MCF51JU128 Data Sheet, Rev. 4, 01/2012.
36
Freescale Semiconductor, Inc.
FREESCALE [ Freescale ]
