Electrical Characteristics
A.3.1.13 Set Field Margin Level (FCMD=0x0E)
The maximum set field margin level time is given by:
1
--------------------
t = 350 ⋅
fNVMBUS
A.3.1.14 Erase Verify D-Flash Section (FCMD=0x10)
The time required to Erase Verify D-Flash for a given number of words N is given by:
W
1
--------------------
tdcheck ≈ (450 + NW) ⋅
fNVMBUS
A.3.1.15 Program D-Flash (FCMD=0x11)
D-Flash programming time is dependent on the number of words being programmed and their location
with respect to a row boundary since programming across a row boundary requires extra steps. The D-
Flash programming time is specified for different cases: 1,2,3,4 words and 4 words across a row boundary.
The typical D-Flash programming time is given by the following equation, where N denotes the number
W
of words; BC=0 if no row boundary is crossed and BC=1 if a row boundary is crossed:
1
1
⎛
⎞
⎠
⎛
⎞
⎠
------------------
fNVMOP
--------------------
fNVMBUS
tdpgm ≈ (14 + (54 ⋅ NW) + (14 ⋅ BC)) ⋅
+ (500 + (525 ⋅ NW) + (100 ⋅ BC)) ⋅
⎝
⎝
The maximum D-Flash programming time is given by:
1
1
⎛
⎞
⎠
⎛
⎞
⎠
------------------
fNVMOP
--------------------
tdpgm ≈ (14 + (54 ⋅ NW) + (14 ⋅ BC)) ⋅
+ (500 + (750 ⋅ NW ) + (100 ⋅ BC)) ⋅
⎝
⎝
fNVMBUS
A.3.1.16 Erase D-Flash Sector (FCMD=0x12)
Typical D-Flash sector erase times, expected on a new device where no margin verify fails occur, is given
by:
1
1
tdera ≈ 5025 ⋅ ------------------ + 700 ⋅
fNVMOP
--------------------
fNVMBUS
Maximum D-Flash sector erase times is given by:
1
1
tdera ≈ 20100 ⋅ ------------------ + 3400 ⋅
fNVMOP
--------------------
fNVMBUS
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
521
FREESCALE [ Freescale ]
