128 KByte Flash Module (S12FTMRC128K1V1)
Table 13-7. FDIV values for various BUSCLK Frequencies
BUSCLK Frequency
(MHz)
BUSCLK Frequency
(MHz)
FDIV[5:0]
FDIV[5:0]
MIN(1)
MAX(2)
MIN1
MAX2
1.0
1.6
1.6
2.6
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
16.6
17.6
18.6
19.6
20.6
21.6
22.6
23.6
24.6
25.6
26.6
27.6
28.6
29.6
30.6
31.6
17.6
18.6
19.6
20.6
21.6
22.6
23.6
24.6
25.6
26.6
27.6
28.6
29.6
30.6
31.6
32.6
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
2.6
3.6
3.6
4.6
4.6
5.6
5.6
6.6
6.6
7.6
7.6
8.6
8.6
9.6
9.6
10.6
11.6
12.6
13.6
14.6
15.6
16.6
10.6
11.6
12.6
13.6
14.6
15.6
1. BUSCLK is Greater Than this value.
2. BUSCLK is Less Than or Equal to this value.
13.3.2.2 Flash Security Register (FSEC)
The FSEC register holds all bits associated with the security of the MCU and Flash module.
Offset Module Base + 0x0001
7
6
5
4
3
2
1
0
R
W
KEYEN[1:0]
RNV[5:2]
SEC[1:0]
Reset
F
F
F
F
F
F
F
F
= Unimplemented or Reserved
Figure 13-6. Flash Security Register (FSEC)
All bits in the FSEC register are readable but not writable.
During the reset sequence, the FSEC register is loaded with the contents of the Flash security byte in the
Flash configuration field at global address 0x3_FF0F located in P-Flash memory (see Table 13-3) as
indicated by reset condition F in Figure 13-6. If a double bit fault is detected while reading the P-Flash
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
435
FREESCALE [ Freescale ]
