128 KByte Flash Module (S12FTMRC128K1V1)
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R
W
FDIVLD
FDIVLCK
FDIV[5:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 13-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field.
CAUTION
The FCLKDIV register must never be written to while a Flash command is
executing (CCIF=0). The FCLKDIV register is writable during the Flash
reset sequence even though CCIF is clear.
Table 13-6. FCLKDIV Field Descriptions
Field
Description
7
Clock Divider Loaded
FDIVLD
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
6
Clock Divider Locked
FDIVLCK 0 FDIV field is open for writing
1 FDIV value is locked and cannot be changed. Once the lock bit is set high, only reset can clear this bit and
restore writability to the FDIV field.
5–0
Clock Divider Bits — FDIV[5:0] must be set to effectively divide BUSCLK down to 1 MHz to control timed events
FDIV[5:0] during Flash program and erase algorithms. Table 13-7 shows recommended values for FDIV[5:0] based on the
BUSCLK frequency. Please refer to Section 13.4.3, “Flash Command Operations,” for more information.
S12P-Family Reference Manual, Rev. 1.13
434
Freescale Semiconductor
FREESCALE [ Freescale ]
