Serial Communication Interface (S12SCIV5)
Start Bit
LSB
RXD
Samples
1
1
1
0
1
1
1
0
0
0
0
0
0
0
RT Clock
RT Clock Count
Reset RT Clock
Figure 11-22. Start Bit Search Example 1
In Figure 11-23, verification sample at RT3 is high. The RT3 sample sets the noise flag. Although the
perceived bit time is misaligned, the data samples RT8, RT9, and RT10 are within the bit time and data
recovery is successful.
Perceived Start Bit
Actual Start Bit
0
LSB
RXD
Samples
1
1
1
1
1
0
1
0
0
0
0
RT Clock
RT Clock Count
Reset RT Clock
Figure 11-23. Start Bit Search Example 2
In Figure 11-24, a large burst of noise is perceived as the beginning of a start bit, although the test sample
at RT5 is high. The RT5 sample sets the noise flag. Although this is a worst-case misalignment of perceived
bit time, the data samples RT8, RT9, and RT10 are within the bit time and data recovery is successful.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
389
FREESCALE [ Freescale ]
