Serial Communication Interface (S12SCIV5)
11.4.6 Receiver
Internal Bus
SBR12:SBR0
Bus
SCI Data Register
Baud Divider
Clock
11-Bit Receive Shift Register
RXPOL
Data
Recovery
H
8
7
6
5
4
3
2
1
0
L
SCRXD
Loop
Control
From TXD Pin
or Transmitter
RE
RAF
FE
NF
PE
LOOPS
RSRC
M
WAKE
ILT
RWU
Wakeup
Logic
PE
PT
R8
Parity
Checking
Idle IRQ
IDLE
ILIE
RDRF/OR
IRQ
BRKDFE
RDRF
OR
RIE
Break
Detect Logic
BRKDIF
BRKDIE
Break IRQ
Active Edge
Detect Logic
RXEDGIF
RXEDGIE
RX Active Edge IRQ
Figure 11-20. SCI Receiver Block Diagram
11.4.6.1 Receiver Character Length
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
11.4.6.2 Character Reception
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data register
is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
S12P-Family Reference Manual, Rev. 1.13
386
Freescale Semiconductor
FREESCALE [ Freescale ]
