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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Serial Communication Interface (S12SCIV5)  
To determine the value of a data bit and to detect noise, recovery logic takes samples at RT8, RT9, and  
RT10. Table 11-18 summarizes the results of the data bit samples.  
Table 11-18. Data Bit Recovery  
RT8, RT9, and RT10 Samples  
Data Bit Determination  
Noise Flag  
000  
001  
010  
011  
100  
101  
110  
111  
0
0
0
1
0
1
1
1
0
1
1
1
1
1
1
0
NOTE  
The RT8, RT9, and RT10 samples do not affect start bit verification. If any  
or all of the RT8, RT9, and RT10 start bit samples are logic 1s following a  
successful start bit verification, the noise flag (NF) is set and the receiver  
assumes that the bit is a start bit (logic 0).  
To verify a stop bit and to detect noise, recovery logic takes samples at RT8, RT9, and RT10. Table 11-19  
summarizes the results of the stop bit samples.  
Table 11-19. Stop Bit Recovery  
RT8, RT9, and RT10 Samples  
Framing Error Flag  
Noise Flag  
000  
001  
010  
011  
100  
101  
110  
111  
1
1
1
0
1
0
0
0
0
1
1
1
1
1
1
0
In Figure 11-22 the verification samples RT3 and RT5 determine that the first low detected was noise and  
not the beginning of a start bit. The RT clock is reset and the start bit search begins again. The noise flag  
is not set because the noise occurred before the start bit was found.  
S12P-Family Reference Manual, Rev. 1.13  
388  
Freescale Semiconductor  
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