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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Serial Communication Interface (S12SCIV5)  
Figure 11-17 shows two cases of break detect. In trace RXD_1 the break symbol starts with the start bit,  
while in RXD_2 the break starts in the middle of a transmission. If BRKDFE = 1, in RXD_1 case there  
will be no byte transferred to the receive buffer and the RDRF flag will not be modified. Also no framing  
error or parity error will be flagged from this transfer. In RXD_2 case, however the break signal starts later  
during the transmission. At the expected stop bit position the byte received so far will be transferred to the  
receive buffer, the receive data register full flag will be set, a framing error and if enabled and appropriate  
a parity error will be set. Once the break is detected the BRKDIF flag will be set.  
Start Bit Position  
Stop Bit Position  
BRKDIF = 1  
RXD_1  
. . .  
10  
Zero Bit Counter  
1
2
3
4
5
6
7
8
9
FE = 1  
BRKDIF = 1  
RXD_2  
. . .  
1
2
3
4
5
6
7
8
9
10  
Zero Bit Counter  
Figure 11-17. Break Detection if BRKDFE = 1 (M = 0)  
11.4.5.4 Idle Characters  
An idle character (or preamble) contains all logic 1s and has no start, stop, or parity bit. Idle character  
length depends on the M bit in SCI control register 1 (SCICR1). The preamble is a synchronizing idle  
character that begins the first transmission initiated after writing the TE bit from 0 to 1.  
If the TE bit is cleared during a transmission, the TXD pin becomes idle after completion of the  
transmission in progress. Clearing and then setting the TE bit during a transmission queues an idle  
character to be sent after the frame currently being transmitted.  
NOTE  
When queueing an idle character, return the TE bit to logic 1 before the stop  
bit of the current frame shifts out through the TXD pin. Setting TE after the  
stop bit appears on TXD causes data previously written to the SCI data  
register to be lost. Toggle the TE bit for a queued idle character while the  
TDRE flag is set and immediately before writing the next byte to the SCI  
data register.  
If the TE bit is clear and the transmission is complete, the SCI is not the  
master of the TXD pin  
S12P-Family Reference Manual, Rev. 1.13  
384  
Freescale Semiconductor  
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