欢迎访问ic37.com |
会员登录 免费注册
发布采购

MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
 浏览型号MC9S12P64CFT的Datasheet PDF文件第366页浏览型号MC9S12P64CFT的Datasheet PDF文件第367页浏览型号MC9S12P64CFT的Datasheet PDF文件第368页浏览型号MC9S12P64CFT的Datasheet PDF文件第369页浏览型号MC9S12P64CFT的Datasheet PDF文件第371页浏览型号MC9S12P64CFT的Datasheet PDF文件第372页浏览型号MC9S12P64CFT的Datasheet PDF文件第373页浏览型号MC9S12P64CFT的Datasheet PDF文件第374页  
Serial Communication Interface (S12SCIV5)  
11.3.2.3 SCI Alternative Status Register 1 (SCIASR1)  
Module Base + 0x0000  
7
6
5
4
3
2
1
0
R
W
0
0
0
0
BERRV  
RXEDGIF  
BERRIF  
BKDIF  
Reset  
0
0
0
0
0
0
0
0
= Unimplemented or Reserved  
Figure 11-6. SCI Alternative Status Register 1 (SCIASR1)  
Read: Anytime, if AMAP = 1  
Write: Anytime, if AMAP = 1  
Table 11-6. SCIASR1 Field Descriptions  
Description  
Field  
7
Receive Input Active Edge Interrupt Flag — RXEDGIF is asserted, if an active edge (falling if RXPOL = 0,  
RXEDGIF rising if RXPOL = 1) on the RXD input occurs. RXEDGIF bit is cleared by writing a “1” to it.  
0 No active receive on the receive input has occurred  
1 An active edge on the receive input has occurred  
2
Bit Error Value — BERRV reflects the state of the RXD input when the bit error detect circuitry is enabled and  
a mismatch to the expected value happened. The value is only meaningful, if BERRIF = 1.  
0 A low input was sampled, when a high was expected  
BERRV  
1 A high input reassembled, when a low was expected  
1
Bit Error Interrupt Flag — BERRIF is asserted, when the bit error detect circuitry is enabled and if the value  
sampled at the RXD input does not match the transmitted value. If the BERRIE interrupt enable bit is set an  
interrupt will be generated. The BERRIF bit is cleared by writing a “1” to it.  
0 No mismatch detected  
BERRIF  
1 A mismatch has occurred  
0
Break Detect Interrupt Flag — BKDIF is asserted, if the break detect circuitry is enabled and a break signal is  
BKDIF  
received. If the BKDIE interrupt enable bit is set an interrupt will be generated. The BKDIF bit is cleared by writing  
a “1” to it.  
0 No break signal was received  
1 A break signal was received  
11.3.2.4 SCI Alternative Control Register 1 (SCIACR1)  
Module Base + 0x0001  
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
RXEDGIE  
BERRIE  
BKDIE  
Reset  
0
0
0
0
0
0
0
0
= Unimplemented or Reserved  
Figure 11-7. SCI Alternative Control Register 1 (SCIACR1)  
Read: Anytime, if AMAP = 1  
Write: Anytime, if AMAP = 1  
S12P-Family Reference Manual, Rev. 1.13  
370  
Freescale Semiconductor  
 复制成功!