Serial Communication Interface (S12SCIV5)
11.3.1 Module Memory Map and Register Definition
The memory map for the SCI module is given below in Figure 11-2. The address listed for each register is
the address offset. The total address for each register is the sum of the base address for the SCI module and
the address offset for each register.
11.3.2 Register Descriptions
This section consists of register descriptions in address order. Each description includes a standard register
diagram with an associated figure number. Writes to a reserved register locations do not have any effect
and reads of these locations return a zero. Details of register bit and field function follow the register
diagrams, in bit order.
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x0000
R
SCIBDH1
IREN
TNP1
TNP0
SBR12
SBR11
SBR10
SBR9
SBR8
W
0x0001
R
SCIBDL1
SBR7
LOOPS
SBR6
SBR5
SBR4
SBR3
SBR2
ILT
SBR1
PE
SBR0
PT
W
0x0002
R
SCICR11
SCISWAI
0
RSRC
0
M
0
WAKE
0
W
0x0000
R
SCIASR12
RXEDGIF
BERRV
0
BERRIF
BERRIE
BERRM0
BKDIF
BKDIE
BKDFE
W
0x0001
R
0
0
0
0
0
0
0
0
SCIACR12
RXEDGIE
0
W
0x0002
R
SCIACR22
BERRM1
W
0x0003
SCICR2
R
TIE
TCIE
TC
RIE
ILIE
TE
RE
NF
RWU
FE
SBK
PF
W
0x0004
R
TDRE
RDRF
IDLE
OR
SCISR1
W
0x0005
SCISR2
R
0
0
RAF
AMAP
TXPOL
RXPOL
BRK13
TXDIR
W
= Unimplemented or Reserved
Figure 11-2. SCI Register Summary (Sheet 1 of 2)
S12P-Family Reference Manual, Rev. 1.13
366
Freescale Semiconductor
FREESCALE [ Freescale ]
