Serial Communication Interface (S12SCIV5)
Table 11-7. SCIACR1 Field Descriptions
Description
Field
7
Receive Input Active Edge Interrupt Enable — RXEDGIE enables the receive input active edge interrupt flag,
RSEDGIE RXEDGIF, to generate interrupt requests.
0 RXEDGIF interrupt requests disabled
1 RXEDGIF interrupt requests enabled
1
Bit Error Interrupt Enable — BERRIE enables the bit error interrupt flag, BERRIF, to generate interrupt
BERRIE
requests.
0 BERRIF interrupt requests disabled
1 BERRIF interrupt requests enabled
0
Break Detect Interrupt Enable — BKDIE enables the break detect interrupt flag, BKDIF, to generate interrupt
BKDIE
requests.
0 BKDIF interrupt requests disabled
1 BKDIF interrupt requests enabled
11.3.2.5 SCI Alternative Control Register 2 (SCIACR2)
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
BERRM1
BERRM0
BKDFE
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 11-8. SCI Alternative Control Register 2 (SCIACR2)
Read: Anytime, if AMAP = 1
Write: Anytime, if AMAP = 1
Table 11-8. SCIACR2 Field Descriptions
Description
Field
2:1
Bit Error Mode — Those two bits determines the functionality of the bit error detect feature. See Table 11-9.
BERRM[1:0]
0
Break Detect Feature Enable — BKDFE enables the break detect circuitry.
0 Break detect circuit disabled
BKDFE
1 Break detect circuit enabled
Table 11-9. Bit Error Mode Coding
BERRM1
BERRM0
Function
0
0
0
1
Bit error detect circuit is disabled
Receive input sampling occurs during the 9th time tick of a transmitted bit
(refer to Figure 11-19)
1
1
0
1
Receive input sampling occurs during the 13th time tick of a transmitted bit
(refer to Figure 11-19)
Reserved
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
371
FREESCALE [ Freescale ]
