Pulse-Width Modulator (PWM8B6CV1) Block Description
Module Base + 0x001D
7
6
5
4
3
2
1
0
R
Bit 7
W
6
5
4
3
2
1
Bit 0
Reset
1
1
1
1
1
1
1
1
Figure 10-32. PWM Channel Duty Registers (PWMDTY5)
Read: anytime
Write: anytime
10.3.2.15 PWM Shutdown Register (PWMSDN)
The PWMSDN register provides for the shutdown functionality of the PWM module in the emergency
cases.
Module Base + 0x00E
7
6
5
4
3
2
1
0
R
W
0
0
PWM5IN
PWMIF
PWMIE
PWMLVL
PWM5INL
PWM5ENA
PWMRSTRT
0
Reset
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-33. PWM Shutdown Register (PWMSDN)
Read: anytime
Write: anytime
Table 10-10. PWMSDN Field Descriptions
Description
Field
7
PWM Interrupt Flag — Any change from passive to asserted (active) state or from active to passive state will be
flagged by setting the PWMIF flag = 1. The flag is cleared by writing a logic 1 to it. Writing a 0 has no effect.
0 No change on PWM5IN input.
PWMIF
1 Change on PWM5IN input
6
PWM Interrupt Enable — If interrupt is enabled an interrupt to the CPU is asserted.
0 PWM interrupt is disabled.
PWMIE
1 PWM interrupt is enabled.
5
PWM Restart — The PWM can only be restarted if the PWM channel input 5 is deasserted. After writing a logic 1
PWMRSTRT to the PWMRSTRT bit (trigger event) the PWM channels start running after the corresponding counter passes
next “counter = 0” phase.
Also, if the PWM5ENA bit is reset to 0, the PWM do not start before the counter passes 0x0000.
The bit is always read as 0.
4
PWM Shutdown Output Level — If active level as defined by the PWM5IN input, gets asserted all enabled PWM
PWMLVL channels are immediately driven to the level defined by PWMLVL.
0 PWM outputs are forced to 0
1 PWM outputs are forced to 1.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
351
FREESCALE [ Freescale ]
