Pulse-Width Modulator (PWM8B6CV1) Block Description
Module Base + 0x00011
7
6
5
4
3
2
1
0
R
W
Bit 7
6
5
4
3
2
1
Bit 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Reset
Figure 10-20. PWM Channel Counter Registers (PWMCNT5)
Read: anytime
Write: anytime (any value written causes PWM counter to be reset to 0x0000).
10.3.2.13 PWM Channel Period Registers (PWMPERx)
There is a dedicated period register for each channel. The value in this register determines the period of
the associated PWM channel.
The period registers for each channel are double buffered so that if they change while the channel is
enabled, the change will NOT take effect until one of the following occurs:
•
•
•
The effective period ends
The counter is written (counter resets to 0x0000)
The channel is disabled
In this way, the output of the PWM will always be either the old waveform or the new waveform, not some
variation in between. If the channel is not enabled, then writes to the period register will go directly to the
latches as well as the buffer.
NOTE
Reads of this register return the most recent value written. Reads do not
necessarily return the value of the currently active period due to the double
buffering scheme.
Reference Section 10.4.2.3, “PWM Period and Duty,” for more information.
To calculate the output period, take the selected clock source period for the channel of interest (A, B, SA,
or SB) and multiply it by the value in the period register for that channel:
•
•
•
Left aligned output (CAEx = 0)
PWMx period = channel clock period * PWMPERx center aligned output (CAEx = 1)
PWMx period = channel clock period * (2 * PWMPERx)
For boundary case programming values, please refer to Section 10.4.2.8, “PWM Boundary Cases.”
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
347
FREESCALE [ Freescale ]
