Pulse-Width Modulator (PWM8B6CV1) Block Description
NOTE
Changing clock control bits while channels are operating can cause
irregularities in the PWM outputs.
10.4.2 PWM Channel Timers
The main part of the PWM module are the actual timers. Each of the timer channels has a counter, a period
register and a duty register (each are 8 bit). The waveform output period is controlled by a match between
the period register and the value in the counter. The duty is controlled by a match between the duty register
and the counter value and causes the state of the output to change during the period. The starting polarity
of the output is also selectable on a per channel basis. Figure 10-35 shows a block diagram for PWM timer.
Clock Source
From Port PWMP
Data Register
8-Bit Counter
GATE
PWMCNTx
(clock edge sync)
8-Bit Compare =
up/down reset
M
U
X
M
U
X
T
Q
Q
PWMDTYx
To Pin
Driver
R
8-Bit Compare =
PWMPERx
PPOLx
T
Q
Q
CAEx
R
PWMEx
Figure 10-35. PWM Timer Channel Block Diagram
10.4.2.1 PWM Enable
Each PWM channel has an enable bit (PWMEx) to start its waveform output. When any of the PWMEx
bits are set (PWMEx = 1), the associated PWM output signal is enabled immediately. However, the actual
PWM waveform is not available on the associated PWM output until its clock source begins its next cycle
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
355
FREESCALE [ Freescale ]
