Pulse-Width Modulator (PWM8B6CV1) Block Description
Module Base + 0x0004
7
6
5
4
3
2
1
0
R
W
0
0
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-7. PWM Center Align Enable Register (PWMCAE)
Read: anytime
Write: anytime
NOTE
Write these bits only when the corresponding channel is disabled.
Table 10-8. PWMCAE Field Descriptions
Description
Field
5
Center Aligned Output Mode on Channel 5
0 Channel 5 operates in left aligned output mode.
1 Channel 5 operates in center aligned output mode.
CAE5
4
Center Aligned Output Mode on Channel 4
0 Channel 4 operates in left aligned output mode.
1 Channel 4 operates in center aligned output mode.
CAE4
3
Center Aligned Output Mode on Channel 3
1 Channel 3 operates in left aligned output mode.
1 Channel 3 operates in center aligned output mode.
CAE3
2
Center Aligned Output Mode on Channel 2
0 Channel 2 operates in left aligned output mode.
1 Channel 2 operates in center aligned output mode.
CAE2
1
Center Aligned Output Mode on Channel 1
0 Channel 1 operates in left aligned output mode.
1 Channel 1 operates in center aligned output mode.
CAE1
0
Center Aligned Output Mode on Channel 0
0 Channel 0 operates in left aligned output mode.
1 Channel 0 operates in center aligned output mode.
CAE0
10.3.2.6 PWM Control Register (PWMCTL)
The PWMCTL register provides for various control of the PWM module.
S12P-Family Reference Manual, Rev. 1.13
340
Freescale Semiconductor
FREESCALE [ Freescale ]
