Pulse-Width Modulator (PWM8B6CV1) Block Description
Module Base + 0x0005
7
6
5
4
3
2
1
0
R
W
0
0
0
CON45
CON23
CON01
PSWAI
PFRZ
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-8. PWM Control Register (PWMCTL)
Read: anytime
Write: anytime
There are three control bits for concatenation, each of which is used to concatenate a pair of PWM
channels into one 16-bit channel. When channels 4 and 5 are concatenated, channel 4 registers become the
high-order bytes of the double-byte channel. When channels 2 and 3 are concatenated, channel 2 registers
become the high-order bytes of the double-byte channel. When channels 0 and 1 are concatenated,
channel 0 registers become the high-order bytes of the double-byte channel.
Reference Section 10.4.2.7, “PWM 16-Bit Functions,” for a more detailed description of the concatenation
PWM function.
NOTE
Change these bits only when both corresponding channels are disabled.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
341
FREESCALE [ Freescale ]
