Pulse-Width Modulator (PWM8B6CV1) Block Description
Table 10-4. PWMCLK Field Descriptions
Field
Description
5
Pulse Width Channel 5 Clock Select
PCLK5
0 Clock A is the clock source for PWM channel 5.
1 Clock SA is the clock source for PWM channel 5.
4
Pulse Width Channel 4 Clock Select
PCLK4
0 Clock A is the clock source for PWM channel 4.
1 Clock SA is the clock source for PWM channel 4.
3
Pulse Width Channel 3 Clock Select
PCLK3
0 Clock B is the clock source for PWM channel 3.
1 Clock SB is the clock source for PWM channel 3.
2
Pulse Width Channel 2 Clock Select
PCLK2
0 Clock B is the clock source for PWM channel 2.
1 Clock SB is the clock source for PWM channel 2.
1
Pulse Width Channel 1 Clock Select
PCLK1
0 Clock A is the clock source for PWM channel 1.
1 Clock SA is the clock source for PWM channel 1.
0
Pulse Width Channel 0 Clock Select
PCLK0
0 Clock A is the clock source for PWM channel 0.
1 Clock SA is the clock source for PWM channel 0.
10.3.2.4 PWM Prescale Clock Select Register (PWMPRCLK)
This register selects the prescale clock source for clocks A and B independently.
Module Base + 0x0003
7
6
5
4
3
2
1
0
R
W
0
0
PCKB2
PCKB1
PCKB0
PCKA2
PCKA1
PCKA0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-6. PWM Prescaler Clock Select Register (PWMPRCLK)
Read: anytime
Write: anytime
NOTE
PCKB2–PCKB0 and PCKA2–PCKA0 register bits can be written anytime.
If the clock prescale is changed while a PWM signal is being generated, a
truncated or stretched pulse can occur during the transition.
S12P-Family Reference Manual, Rev. 1.13
338
Freescale Semiconductor
FREESCALE [ Freescale ]
