Pulse-Width Modulator (PWM8B6CV1) Block Description
Table 10-3. PWMPOL Field Descriptions (continued)
Field
Description
3
Pulse Width Channel 3 Polarity
PPOL3
0 PWM channel 3 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 3 output is high at the beginning of the period, then goes low when the duty count is reached.
2
Pulse Width Channel 2 Polarity
PPOL2
0 PWM channel 2 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 2 output is high at the beginning of the period, then goes low when the duty count is reached.
1
Pulse Width Channel 1 Polarity
PPOL1
0 PWM channel 1 output is low at the beginning of the period, then goes high when the duty count is reached.
1 PWM channel 1 output is high at the beginning of the period, then goes low when the duty count is reached.
0
Pulse Width Channel 0 Polarity
PPOL0
0 PWM channel 0 output is low at the beginning of the period, then goes high when the duty count is reached
1 PWM channel 0 output is high at the beginning of the period, then goes low when the duty count is reached.
10.3.2.3 PWM Clock Select Register (PWMCLK)
Each PWM channel has a choice of two clocks to use as the clock source for that channel as described
below.
Module Base + 0x0002
7
6
5
4
3
2
1
0
R
W
0
0
PCLK5
PCLK4
PCLK3
PCLK2
PCLK1
PCLK0
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 10-5. PWM Clock Select Register (PWMCLK)
Read: anytime
Write: anytime
NOTE
Register bits PCLK0 to PCLK5 can be written anytime. If a clock select is
changed while a PWM signal is being generated, a truncated or stretched
pulse can occur during the transition.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
337
FREESCALE [ Freescale ]
