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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Pulse-Width Modulator (PWM8B6CV1) Block Description  
Table 10-2. PWME Field Descriptions (continued)  
Field  
Description  
1
Pulse Width Channel 1 Enable  
PWME1  
0 Pulse width channel 1 is disabled.  
1 Pulse width channel 1 is enabled. The pulse modulated signal becomes available at PWM, output bit 1 when  
its clock source begins its next cycle.  
0
Pulse Width Channel 0 Enable  
PWME0  
0 Pulse width channel 0 is disabled.  
1 Pulse width channel 0 is enabled. The pulse modulated signal becomes available at PWM, output bit 0 when  
its clock source begins its next cycle. If CON01 = 1, then bit has no effect and PWM output line 0 is disabled.  
10.3.2.2 PWM Polarity Register (PWMPOL)  
The starting polarity of each PWM channel waveform is determined by the associated PPOLx bit in the  
PWMPOL register. If the polarity bit is 1, the PWM channel output is high at the beginning of the cycle  
and then goes low when the duty count is reached. Conversely, if the polarity bit is 0 the output starts low  
and then goes high when the duty count is reached.  
Module Base + 0x0001  
7
6
5
4
3
2
1
0
R
W
0
0
PPOL5  
PPOL4  
PPOL3  
PPOL2  
PPOL1  
PPOL0  
Reset  
0
0
0
0
0
0
0
0
= Unimplemented or Reserved  
Figure 10-4. PWM Polarity Register (PWMPOL)  
Read: anytime  
Write: anytime  
NOTE  
PPOLx register bits can be written anytime. If the polarity is changed while  
a PWM signal is being generated, a truncated or stretched pulse can occur  
during the transition  
Table 10-3. PWMPOL Field Descriptions  
Description  
Field  
5
Pulse Width Channel 5 Polarity  
PPOL5  
0 PWM channel 5 output is low at the beginning of the period, then goes high when the duty count is reached.  
1 PWM channel 5 output is high at the beginning of the period, then goes low when the duty count is reached.  
4
Pulse Width Channel 4 Polarity  
PPOL4  
0 PWM channel 4 output is low at the beginning of the period, then goes high when the duty count is reached.  
1 PWM channel 4 output is high at the beginning of the period, then goes low when the duty count is reached.  
S12P-Family Reference Manual, Rev. 1.13  
336  
Freescale Semiconductor  
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