Analog-to-Digital Converter (ADC12B10C)
9.3.2.11 ATD Compare Higher Than Register (ATDCMPHT)
Writes to this register will abort current conversion sequence.
Read: Anytime
Write: Anytime
Module Base + 0x000E
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
CMPHT[9:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-13. ATD Compare Higher Than Register (ATDCMPHT)
Table 9-20. ATDCMPHT Field Descriptions
Description
Field
9–0
Compare Operation Higher Than Enable for conversion number n (n= 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a
CMPHT[9:0] Sequence (n conversion number, NOT channel number!) — This bit selects the operator for comparison of
conversion results.
0 If result of conversion n is lower or same than compare value in ATDDRn, this is flagged in ATDSTAT2
1 If result of conversion n is higher than compare value in ATDDRn, this is flagged in ATDSTAT2
9.3.2.12 ATD Conversion Result Registers (ATDDRn)
The A/D conversion results are stored in 10 result registers. Results are always in unsigned data
representation. Left and right justification is selected using the DJM control bit in ATDCTL3.
If automatic compare of conversions results is enabled (CMPE[n]=1 in ATDCMPE), these registers must
be written with the compare values in left or right justified format depending on the actual value of the
DJM bit. In this case, as the ATDDRn register is used to hold the compare value, the result will not be
stored there at the end of the conversion but is lost.
Attention, n is the conversion number, NOT the channel number!
Read: Anytime
Write: Anytime
NOTE
For conversions not using automatic compare, results are stored in the result
registers after each conversion. In this case avoid writing to ATDDRn except
for initial values, because an A/D result might be overwritten.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
323
FREESCALE [ Freescale ]
