Analog-to-Digital Converter (ADC12B10C)
be edge or level sensitive with polarity control. Table 9-22 gives a brief description of the different
combinations of control bits and their effect on the external trigger function.
Table 9-22. External Trigger Control Bits
ETRIGLE
ETRIGP
ETRIGE
SCAN
Description
X
X
0
0
Ignores external trigger. Performs one
conversion sequence and stops.
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
1
X
X
X
X
Ignores external trigger. Performs
continuous conversion sequences.
Falling edge triggered. Performs one
conversion sequence per trigger.
Rising edge triggered. Performs one
conversion sequence per trigger.
Trigger active low. Performs continuous
conversions while trigger is active.
Trigger active high. Performs continuous
conversions while trigger is active.
During a conversion, if additional active edges are detected the overrun error flag ETORF is set.
In either level or edge triggered modes, the first conversion begins when the trigger is received.
Once ETRIGE is enabled, conversions cannot be started by a write to ATDCTL5, but rather must be
triggered externally.
If the level mode is active and the external trigger both de-asserts and re-asserts itself during a conversion
sequence, this does not constitute an overrun. Therefore, the flag is not set. If the trigger is left asserted in
level mode while a sequence is completing, another sequence will be triggered immediately.
9.4.2.2
General-Purpose Digital Port Operation
The input channel pins can be multiplexed between analog and digital data. As analog inputs, they are
multiplexed and sampled as analog channels to the A/D converter. The analog/digital multiplex operation
is performed in the input pads. The input pad is always connected to the analog input channels of the
ADC12B10C. The input pad signal is buffered to the digital port registers. This buffer can be turned on or
off with the ATDDIEN register. This is important so that the buffer does not draw excess current when
analog potentials are presented at its input.
9.5
Resets
At reset the ADC12B10C is in a power down state. The reset state of each individual bit is listed within
the Register Description section (see Section 9.3.2, “Register Descriptions”) which details the registers
and their bit-field.
S12P-Family Reference Manual, Rev. 1.13
326
Freescale Semiconductor
FREESCALE [ Freescale ]
