Analog-to-Digital Converter (ADC12B10C)
Module Base + 0x0008
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
CMPE[9:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-10. ATD Compare Enable Register (ATDCMPE)
Table 9-17. ATDCMPE Field Descriptions
Description
Field
9–0
Compare Enable for Conversion Number n (n= 9, 8, 7, 6, 5, 4, 3, 2, 1, 0) of a Sequence (n conversion
CMPE[9:0] number, NOT channel number!) — These bits enable automatic compare of conversion results individually for
conversions of a sequence. The sense of each comparison is determined by the CMPHT[n] bit in the ATDCMPHT
register.
For each conversion number with CMPE[n]=1 do the following:
1) Write compare value to ATDDRn result register
2) Write compare operator with CMPHT[n] in ATDCPMHT register
CCF[n] in ATDSTAT2 register will flag individual success of any comparison.
0 No automatic compare
1 Automatic compare of results for conversion n of a sequence is enabled.
9.3.2.9
ATD Status Register 2 (ATDSTAT2)
This read-only register contains the Conversion Complete Flags CCF[9:0].
Module Base + 0x000A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
W
0
0
0
0
0
0
CCF[9:0]
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-11. ATD Status Register 2 (ATDSTAT2)
Read: Anytime
Write: Anytime, no effect
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
321
FREESCALE [ Freescale ]
