Analog-to-Digital Converter (ADC12B10C)
Table 9-15. Analog Input Channel Select Coding
Analog Input
Channel
SC
CD
CC
CB
CA
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
0
1
0
1
X
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
AN8
AN9
AN9
AN9
AN9
AN9
AN9
AN9
1
Reserved
SPECIAL17
Reserved
VRH
VRL
(VRH+VRL) / 2
Reserved
Reserved
9.3.2.7
ATD Status Register 0 (ATDSTAT0)
This register contains the Sequence Complete Flag, overrun flags for external trigger and FIFO mode, and
the conversion counter.
Module Base + 0x0006
7
6
5
4
3
2
1
0
R
W
0
CC3
CC2
CC1
CC0
SCF
ETORF
FIFOR
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 9-9. ATD Status Register 0 (ATDSTAT0)
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
319
FREESCALE [ Freescale ]
