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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Analog-to-Digital Converter (ADC12B10C)  
9.4.1  
Analog Sub-Block  
The analog sub-block contains all analog electronics required to perform a single conversion. Separate  
power supplies V and V allow to isolate noise of other MCU circuitry from the analog sub-block.  
DDA  
SSA  
9.4.1.1  
Sample and Hold Machine  
The Sample and Hold (S/H) Machine accepts analog signals from the external world and stores them as  
capacitor charge on a storage node.  
During the sample process the analog input connects directly to the storage node.  
The input analog signals are unipolar and must fall within the potential range of V  
During the hold process the analog input is disconnected from the storage node.  
to V  
.
DDA  
SSA  
9.4.1.2  
Analog Input Multiplexer  
The analog input multiplexer connects one of the 10 external analog input channels to the sample and hold  
machine.  
9.4.1.3  
Analog-to-Digital (A/D) Machine  
The A/D Machine performs analog to digital conversions. The resolution is program selectable at either 8  
or 10 or 12 bits. The A/D machine uses a successive approximation architecture. It functions by comparing  
the stored analog sample potential with a series of digitally generated analog potentials. By following a  
binary search algorithm, the A/D machine locates the approximating potential that is nearest to the  
sampled potential.  
When not converting the A/D machine is automatically powered down.  
Only analog input signals within the potential range of V to V (A/D reference potentials) will result  
RL  
RH  
in a non-railed digital output code.  
9.4.2  
Digital Sub-Block  
This subsection explains some of the digital features in more detail. See Section 9.3.2, “Register  
Descriptions” for all details.  
9.4.2.1  
External Trigger Input  
The external trigger feature allows the user to synchronize ATD conversions to the external environment  
events rather than relying on software to signal the ATD module when ATD conversions are to take place.  
The external trigger signal (out of reset ATD channel 9, configurable in ATDCTL1) is programmable to  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
325  
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