Analog-to-Digital Converter (ADC12B10C)
Table 9-11. ATD Behavior in Freeze Mode (Breakpoint)
FRZ1
FRZ0
Behavior in Freeze Mode
0
1
1
1
0
1
Reserved
Finish current conversion, then freeze
Freeze Immediately
9.3.2.5
ATD Control Register 4 (ATDCTL4)
Writes to this register will abort current conversion sequence.
Module Base + 0x0004
7
6
5
4
3
2
1
0
R
W
SMP2
SMP1
SMP0
PRS[4:0]
Reset
0
0
0
0
0
1
0
1
Figure 9-7. ATD Control Register 4 (ATDCTL4)
Read: Anytime
Write: Anytime
Table 9-12. ATDCTL4 Field Descriptions
Description
Field
7–5
Sample Time Select — These three bits select the length of the sample time in units of ATD conversion clock
SMP[2:0] cycles. Note that the ATD conversion clock period is itself a function of the prescaler value (bits PRS4-0). Table 9-
13 lists the available sample time lengths.
4–0
ATD Clock Prescaler — These 5 bits are the binary prescaler value PRS. The ATD conversion clock frequency
PRS[4:0]
is calculated as follows:
f
BUS
f
= -------------------------------------
ATDCLK
2 × (PRS + 1)
Refer to Device Specification for allowed frequency range of fATDCLK
.
Table 9-13. Sample Time Select
Sample Time
in Number of
SMP2
SMP1
SMP0
ATD Clock Cycles
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4
6
8
10
12
16
20
24
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
317
FREESCALE [ Freescale ]
