S12 Clock, Reset and Power Management Unit (S12CPMU)
Windowed COP operation is enabled by setting WCOP in the CPMUCOP register. In this mode, writes to
the CPMUARMCOP register to clear the COP timer must occur in the last 25% of the selected time-out
period. A premature write will immediately reset the part.
7.5.3
Power-On Reset (POR)
The on-chip POR circuitry detects when the internal supply V drops below an appropriate voltage level
DD
(voltage level not specified in this document because this supply is not visible on device pins). POR is
deasserted, if the internal supply V exceeds an appropriate voltage level (voltage level not specified in
DD
this document because this supply is not visible on device pins).
7.5.4
Low-Voltage Reset (LVR)
The on-chip LVR circuitry detects when one of the supply voltages V , V
or V
drops below an
DD
DDF
DDX
appropriate voltage level. If LVR is deasserted the MCU is fully operational at the specified maximum
speed.The LVR assert and deassert levels for the supply voltage VDDX are V
specified in the device Reference Manual.
and V
and are
LVRXA
LVRXD
7.6
Interrupts
The interrupt/reset vectors requested by the S12CPMU are listed in Table 7-27. Refer to MCU
specification for related vector addresses and priorities.
Table 7-27. S12CPMU Interrupt Vectors
CCR
Interrupt Source
Local Enable
Mask
RTI time-out interrupt
PLL lock interrupt
I bit
CPMUINT (RTIE)
I bit
CPMUINT (LOCKIE)
Oscillator status
interrupt
I bit
CPMUINT (OSCIE)
Low voltage interrupt
I bit
I bit
CPMULVCTL (LVIE)
CPMUHTCTL (HTIE)
High temperature
interrupt
Autonomous
Periodical Interrupt
I bit
CPMUAPICTL (APIE)
S12P-Family Reference Manual, Rev. 1.13
248
Freescale Semiconductor
FREESCALE [ Freescale ]
