S12 Clock, Reset and Power Management Unit (S12CPMU)
7.4.6.3
PLL Bypassed External Mode (PBE)
In this mode, the Bus Clock is based on the external oscillator clock. The reference clock for the PLL is
based on the external oscillator. The adaptive spike filter and detection logic can be enabled which uses
the VCOCLK to filter and qualify the external oscillator clock.
The clock sources for COP and RTI can be based on the internal reference clock generator or on the
external oscillator clock.
This mode can be entered from default mode PEI by performing the following steps:
1. Make sure the PLL configuration is valid
2. Optionally the adaptive spike filter and detection logic can be enabled by calculating the integer
value for the OSCFIL[4:0] bits and setting the bandwidth (OSCBW) accordingly.
3. Enable the external oscillator (OSCE bit)
4. Wait for the PLL being locked (LOCK = 1) and the oscillator to start-up and additionally being
qualified if the adaptive spike filter is enabled (UPOSC =1).
5. Clear all flags in the CPMUFLG register to be able to detect any status bit change.
6. Optionally status interrupts can be enabled (CPMUINT register).
7. Select the Oscillator Clock (OSCCLK) as Bus Clock (PLLSEL=0)
Since the adaptive spike filter (filter and detection logic) uses VCOCLK (from PLL) to continuously filter
and qualify the external oscillator clock, loosing PLL lock status (LOCK=0) means loosing the oscillator
status information as well (UPOSC=0).
The impact of loosing the oscillator status in PBE mode is as follows:
•
•
PLLSEL is set automatically and the Bus Clock is switched back to the PLLCLK.
The PLLCLK is derived from the VCO clock (with its actual frequency) divided by four until the
PLL locks again.
Application software needs to be prepared to deal with the impact of loosing the oscillator status at any
time.
In the PBE mode, not every noise disturbance can be indicated by bits LOCK and UPOSC (both bits are
based on the Bus Clock domain). There are clock disturbances possible, after which UPOSC and LOCK
both stay asserted while occasional pauses on the filtered OSCCLK and resulting Bus Clock occur. The
spike filter is still functional and protects the Bus Clock from frequency overshoot due to spikes on the
external oscillator clock. The filtered OSCCLK and resulting Bus Clock will pause until the PLL has
stabilized again.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
245
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