S12 Clock, Reset and Power Management Unit (S12CPMU)
7.5
Resets
General
7.5.1
All reset sources are listed in Table 7-25. Refer to MCU specification for related vector addresses and
priorities.
Table 7-25. Reset Summary
Reset Source
Local Enable
Power-On Reset (POR)
Low Voltage Reset (LVR)
External pin RESET
Illegal Address Reset
Clock Monitor Reset
COP Reset
None
None
None
None
OSCE Bit in CPMUOSC register
CR[2:0] in CPMUCOP register
7.5.2
Description of Reset Operation
Upon detection of any reset of Table 7-25, an internal circuit drives the RESET pin low for 512 PLLCLK
cycles. After 512 PLLCLK cycles the RESET pin is released. The reset generator of the S12CPMU waits
for additional 256 PLLCLK cycles and then samples the RESET pin to determine the originating source.
Table 7-26 shows which vector will be fetched.
Table 7-26. Reset Vector Selection
Sampled RESET Pin
(256 cycles after
release)
COP
time out
pending
Oscillator monitor
fail pending
Vector Fetch
1
0
0
POR
LVR
Illegal Address Reset
External pin RESET
1
1
0
1
0
X
X
1
Clock Monitor Reset
COP Reset
X
POR
LVR
Illegal Address Reset
External pin RESET
NOTE
While System Reset is asserted the PLLCLK runs with the frequency
f
.
VCORST
S12P-Family Reference Manual, Rev. 1.13
246
Freescale Semiconductor
FREESCALE [ Freescale ]
