Freescale’s Scalable Controller Area Network (S12MSCANV3)
8.1.1
Glossary
Table 8-2. Terminology
ACK
CAN
Acknowledge of CAN message
Controller Area Network
Cyclic Redundancy Code
End of Frame
CRC
EOF
FIFO
First-In-First-Out Memory
Inter-Frame Sequence
IFS
SOF
Start of Frame
CPU bus
CAN bus
oscillator clock
bus clock
CAN clock
CPU related read/write data bus
CAN protocol related serial bus
Direct clock from external oscillator
CPU bus realated clock
CAN protocol related clock
8.1.2
Block Diagram
MSCAN
CANCLK
Oscillator Clock
Bus Clock
Tq Clk
MUX
Presc.
RXCAN
TXCAN
Receive/
Transmit
Engine
Transmit Interrupt Req.
Receive Interrupt Req.
Errors Interrupt Req.
Wake-Up Interrupt Req.
Message
Filtering
and
Control
and
Status
Buffering
Configuration
Registers
Wake-Up
Low Pass Filter
Figure 8-1. MSCAN Block Diagram
S12P-Family Reference Manual, Rev. 1.13
252
Freescale Semiconductor
FREESCALE [ Freescale ]
