S12 Clock, Reset and Power Management Unit (S12CPMU)
The internal reset of the MCU remains asserted while the reset generator completes the 768 PLLCLK
cycles long reset sequence. In case the RESET pin is externally driven low for more than these 768
PLLCLK cycles (External Reset), the internal reset remains asserted longer.
Figure 7-37. RESET Timing
RESET
S12_CPMU drives
RESET pin low
S12_CPMU releases
RESET pin
f
f
VCORST
VCORST
)
(
)
)
PLLCLK
(
(
512 cycles
256 cycles
possibly
RESET
driven low
externally
7.5.2.1
Clock Monitor Reset
If the external oscillator is enabled (OSCE=1) in case of loss of oscillation or the oscillator frequency is
below the failure assert frequency f (see device electrical characteristics for values), the S12CPMU
CMFA
generates a Clock Monitor Reset.In Full Stop Mode the external oscillator and the clock monitor are
disabled.
7.5.2.2
Computer Operating Properly Watchdog (COP) Reset
The COP (free running watchdog timer) enables the user to check that a program is running and
sequencing properly. When the COP is being used, software is responsible for keeping the COP from
timing out. If the COP times out it is an indication that the software is no longer being executed in the
intended sequence; thus COP reset is generated.
The clock source for the COP is either IRCCLK or OSCCLK depending on the setting of the
COPOSCSEL bit. In Stop Mode with PSTP=1 (Pseudo Stop Mode), COPOSCSEL=1 and PCE=1 the COP
continues to run, else the COP counter halts in Stop Mode.
Three control bits in the CPMUCOP register allow selection of seven COP time-out periods.
When COP is enabled, the program must write $55 and $AA (in this order) to the CPMUARMCOP
register during the selected time-out period. Once this is done, the COP time-out period is restarted. If the
program fails to do this and the COP times out, a COP reset is generated. Also, if any value other than $55
or $AA is written, a COP reset generated.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
247
FREESCALE [ Freescale ]
