Device Overview MC9S12P-Family
1.4
Block Diagram
Figure 1-1 shows a block diagram of the MC9S12P-Family devices
VDDA
VSSA
VRH
ATD
32K/64K/96K/128K bytes Flash
12-bit 10-channel
Analog-Digital Converter
VRL
2K/4K/6K bytes RAM
4K bytes Data Flash
AN[9:0]
PAD[9:0]
IOC0
IOC1
IOC2
IOC3
IOC4
IOC5
IOC6
IOC7
PT0
PT1
PT2
PT3
PT4
PT5
PT6
PT7
TIM
VDDR
VSS3
Voltage Regulator
CPU12-V1
16-bit 8 channel
Timer
Debug Module
Single-wire Background
Debug Module
3 address breakpoints
1 data breakpoints
BKGD
PWM0
PWM1
PWM2
PWM3
PWM4
PWM5
PP0
PP1
PP2
PP3
PP4
PP5
PWM
64 Byte Trace Buffer
Clock Monitor
COP Watchdog
Periodic Interrupt
Auton. Periodic Int.
Amplitude Controlled
Low Power Pierce
Oscillator
8-bit 6channel
Pulse Width Modulator
EXTAL
XTAL
PLL with Frequency
Modulation option
VSSPLLL
RESET
TEST
PP7
Reset Generation
and Test Entry
PM0
PM1
PM2
PM3
PM4
PM5
RXCAN
TXCAN
MISO
SS
MOSI
SCK
CAN
msCAN 2.0B
SPI
Interrupt Module
PE0
XIRQ
IRQ
PE1
PE2
PE3
PE4
PE5
PE6
PE7
Synchronous Serial IF
ECLK
ECLKX2
PS0
PS1
PS2
PS3
RXD
TXD
SCI
Asynchronous Serial IF
PA[7:0]
PB[7:0]
PJ0
PJ1
PJ2
3-5V IO Supply
VDDX1/VSSX1
VDDX2/VSSX2
PJ6
PJ7
Figure 1-1. MC9S12P-Family Block Diagram
S12P-Family Reference Manual, Rev. 1.13
24
Freescale Semiconductor
FREESCALE [ Freescale ]
