Background Debug Module (S12SBDMV1)
Global
Address
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x3_FF05
Reserved
R
X
X
X
X
X
X
X
X
W
0x3_FF06 BDMCCR
R
CCR7
0
CCR6
0
CCR5
0
CCR4
0
CCR3
0
CCR2
0
CCR1
0
CCR0
0
W
0x3_FF07
0x3_FF08
0x3_FF09
Reserved
BDMPPR
Reserved
R
W
R
0
0
0
0
0
0
0
0
0
0
0
0
BPAE
0
BPP3
0
BPP2
0
BPP1
0
BPP0
0
W
R
W
0x3_FF0A Reserved
0x3_FF0B Reserved
R
0
0
0
0
0
0
0
0
0
0
W
R
W
= Unimplemented, Reserved
= Indeterminate
= Implemented (do not alter)
= Always read zero
X
0
Figure 5-2. BDM Register Summary (continued)
5.3.2.1
BDM Status Register (BDMSTS)
Register Global Address 0x3_FF01
7
6
5
4
3
2
1
0
R
BDMACT
0
SDV
TRACE
0
UNSEC
0
ENBDM
W
Reset
Special Single-Chip Mode
All Other Modes
0(1)
0
1
0
0
0
0
0
0
0
0
0
0(2)
0
0
0
= Unimplemented, Reserved
= Implemented (do not alter)
0
= Always read zero
1. ENBDM is read as 1 by a debugging environment in special single chip mode when the device is not secured or secured but
fully erased (Flash). This is because the ENBDM bit is set by the standard BDM firmware before a BDM command can be fully
transmitted and executed.
2. UNSEC is read as 1 by a debugging environment in special single chip mode when the device is secured and fully erased,
else it is 0 and can only be read if not secure (see also bit description).
Figure 5-3. BDM Status Register (BDMSTS)
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
135
FREESCALE [ Freescale ]
