Background Debug Module (S12SBDMV1)
Register Global Address 0x3_FF06
7
6
5
4
3
2
1
0
R
CCR7
CCR6
CCR5
CCR4
CCR3
CCR2
CCR1
CCR0
W
Reset
Special Single-Chip Mode
All Other Modes
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
Figure 5-4. BDM CCR Holding Register (BDMCCR)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
NOTE
When BDM is made active, the CPU stores the content of its CCR register
in the BDMCCR register. However, out of special single-chip reset, the
BDMCCR is set to 0xD8 and not 0xD0 which is the reset value of the CCR
register in this CPU mode. Out of reset in all other modes the BDMCCR
register is read zero.
When entering background debug mode, the BDM CCR holding register is used to save the condition code
register of the user’s program. It is also used for temporary storage in the standard BDM firmware mode.
The BDM CCR holding register can be written to modify the CCR value.
5.3.2.2
BDM Program Page Index Register (BDMPPR)
Register Global Address 0x3_FF08
7
BPAE
0
6
0
5
0
4
0
3
BPP3
0
2
BPP2
0
1
BPP1
0
0
BPP0
0
R
W
Reset
0
0
0
= Unimplemented, Reserved
Figure 5-5. BDM Program Page Register (BDMPPR)
Read: All modes through BDM operation when not secured
Write: All modes through BDM operation when not secured
Table 5-3. BDMPPR Field Descriptions
Field
Description
7
BDM Program Page Access Enable Bit — BPAE enables program page access for BDM hardware and
firmware read/write instructions The BDM hardware commands used to access the BDM registers (READ_BD
and WRITE_BD) can not be used for global accesses even if the BGAE bit is set.
0 BDM Program Paging disabled
BPAE
1 BDM Program Paging enabled
3–0
BDM Program Page Index Bits 3–0 — These bits define the selected program page. For more detailed
BPP[3:0]
information regarding the program page window scheme, please refer to the S12S_MMC Block Guide.
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
137
FREESCALE [ Freescale ]
