Chapter 5
Background Debug Module (S12SBDMV1)
Revision History
Revision Number
s12s_bdm.01.00.00
s12s_bdm.01.00.02
s12s_bdm.01.00.12
s12s_bdm.01.01.01
1.02
Date
Summary of Changes
08.Feb.2006
09.Feb.2006
10.May.2006
20.Sep.2007
08.Apr.2009
14.May.2009
30.Nov.2009
General
General
First version of S12SBDMV1
Updated register address information & Block Version
Removed CLKSW bit and description
Added conditional text for S12P family
Minor text corrections following review
Internal Conditional text only
5.3.2/5-134
General
General
1.03
1.04
Internal Conditional text only
5.1
Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12S
core platform.
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
The BDM has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to determine the communication rate
and a handshake signal to indicate when an operation is complete. The system is backwards compatible to
the BDM of the S12 family with the following exceptions:
•
•
•
•
TAGGO command not supported by S12SBDM
External instruction tagging feature is part of the DBG module
S12SBDM register map and register content modified
Family ID readable from BDM ROM at global address 0x3_FF0F in active BDM
(value for devices with HCS12S core is 0xC2)
•
Clock switch removed from BDM (CLKSW bit removed from BDMSTS register)
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
131
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