Background Debug Module (S12SBDMV1)
5.1.2.3
Low-Power Modes
The BDM can be used until stop mode is entered. When CPU is in wait mode all BDM firmware
commands as well as the hardware BACKGROUND command cannot be used and are ignored. In this case
the CPU can not enter BDM active mode, and only hardware read and write commands are available. Also
the CPU can not enter a low power mode (stop or wait) during BDM active mode.
In stop mode the BDM clocks are stopped. When BDM clocks are disabled and stop mode is exited, the
BDM clocks will restart and BDM will have a soft reset (clearing the instruction register, any command in
progress and disable the ACK function). The BDM is now ready to receive a new command.
5.1.3
Block Diagram
A block diagram of the BDM is shown in Figure 5-1.
Host
System
Serial
Interface
Data
16-Bit Shift Register
BKGD
Control
Register Block
Address
Data
Bus Interface
and
Control Logic
TRACE
Instruction Code
and
Control
Clocks
BDMACT
Execution
ENBDM
SDV
Standard BDM Firmware
LOOKUP TABLE
Secured BDM Firmware
LOOKUP TABLE
UNSEC
BDMSTS
Register
Figure 5-1. BDM Block Diagram
5.2
External Signal Description
A single-wire interface pin called the background debug interface (BKGD) pin is used to communicate
with the BDM system. During reset, this pin is a mode select input which selects between normal and
special modes of operation. After reset, this pin becomes the dedicated serial interface pin for the
background debug mode. The communication rate of this pin is based on the settings for the VCO clock
(CPMUSYNR). The BDM clock frequency is always VCO clock frequency divided by 8. After reset the
BDM clock is based on the reset values of the CPMUSYNR register (4 MHz). When modifying the VCO
S12P-Family Reference Manual, Rev. 1.13
Freescale Semiconductor
133
FREESCALE [ Freescale ]
