Background Debug Module (S12SBDMV1)
clock please make sure that the communication rate is adapted accordingly and a communication time-out
(BDM soft reset) has occurred.
5.3
Memory Map and Register Definition
Module Memory Map
5.3.1
Table 5-1 shows the BDM memory map when BDM is active.
Table 5-1. BDM Memory Map
Size
(Bytes)
Global Address
Module
0x3_FF00–0x3_FF0B
0x3_FF0C–0x3_FF0E
0x3_FF0F
BDM registers
BDM firmware ROM
12
3
Family ID (part of BDM firmware ROM)
BDM firmware ROM
1
0x3_FF10–0x3_FFFF
240
5.3.2
Register Descriptions
A summary of the registers associated with the BDM is shown in Figure 5-2. Registers are accessed by
host-driven communications to the BDM hardware using READ_BD and WRITE_BD commands.
Global
Address
Register
Name
Bit 7
6
5
4
3
2
1
Bit 0
0x3_FF00
0x3_FF01
0x3_FF02
0x3_FF03
0x3_FF04
Reserved
BDMSTS
Reserved
Reserved
Reserved
R
X
X
X
X
X
X
0
0
W
R
BDMACT
0
X
X
X
SDV
X
TRACE
0
X
X
X
UNSEC
0
X
X
X
ENBDM
X
W
R
X
X
X
X
X
X
X
X
X
W
R
X
X
X
W
R
X
W
= Unimplemented, Reserved
= Indeterminate
= Implemented (do not alter)
= Always read zero
X
0
Figure 5-2. BDM Register Summary
S12P-Family Reference Manual, Rev. 1.13
134
Freescale Semiconductor
FREESCALE [ Freescale ]
