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MC9S12P64CFT 参数 Datasheet PDF下载

MC9S12P64CFT图片预览
型号: MC9S12P64CFT
PDF下载: 下载PDF文件 查看货源
内容描述: 微控制器 [Microcontrollers]
分类和应用: 微控制器外围集成电路时钟
文件页数/大小: 566 页 / 7414 K
品牌: FREESCALE [ Freescale ]
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Interrupt Module (S12SINTV1)  
If the interrupt source is unknown (for example, in the case where an interrupt request becomes inactive  
after the interrupt has been recognized, but prior to the CPU vector request), the vector address supplied  
to the CPU will default to that of the spurious interrupt vector.  
NOTE  
Care must be taken to ensure that all interrupt requests remain active until  
the system begins execution of the applicable service routine; otherwise, the  
exception request may not get processed at all or the result may be a  
spurious interrupt request (vector at address (vector base + 0x0080)).  
4.4.3  
Reset Exception Requests  
The INT module supports three system reset exception request types (please refer to the Clock and Reset  
generator module for details):  
1. Pin reset, power-on reset or illegal address reset, low voltage reset (if applicable)  
2. Clock monitor reset request  
3. COP watchdog reset request  
4.4.4  
Exception Priority  
The priority (from highest to lowest) and address of all exception vectors issued by the INT module upon  
request by the CPU is shown in Table 4-4.  
Table 4-4. Exception Vector Map and Priority  
Vector Address(1)  
Source  
0xFFFE  
Pin reset, power-on reset, illegal address reset, low voltage reset (if applicable)  
Clock monitor reset  
0xFFFC  
0xFFFA  
COP watchdog reset  
(Vector base + 0x00F8)  
(Vector base + 0x00F6)  
(Vector base + 0x00F4)  
(Vector base + 0x00F2)  
Unimplemented opcode trap  
Software interrupt instruction (SWI) or BDM vector request  
X bit maskable interrupt request (XIRQ or D2D error interrupt)(2)  
IRQ or D2D interrupt request(3)  
(Vector base + 0x00F0–0x0082) Device specific I bit maskable interrupt sources (priority determined by the low byte of the  
vector address, in descending order)  
(Vector base + 0x0080)  
Spurious interrupt  
1. 16 bits vector address based  
2. D2D error interrupt on MCUs featuring a D2D initiator module, otherwise XIRQ pin interrupt  
3. D2D interrupt on MCUs featuring a D2D initiator module, otherwise IRQ pin interrupt  
S12P-Family Reference Manual, Rev. 1.13  
Freescale Semiconductor  
127  
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