Serial Peripheral Interface Module (SPI)
SPRF — SPI Receiver Full Bit
This clearable, read-only flag is set each time a byte transfers from the shift
register to the receive data register. SPRF generates a CPU interrupt request if
the SPRIE bit in the SPI control register is set also.
During an SPRF CPU interrupt (DMAS = 0), the CPU clears SPRF by reading
the SPI status and control register with SPRF set and then reading the SPI data
register.
Reset clears the SPRF bit.
1 = Receive data register full
0 = Receive data register not full
ERRIE — Error interrupt Enable Bit
This read/write bit enables the MODF and OVRF bits to generate CPU interrupt
requests. Reset clears the ERRIE bit.
1 = MODF and OVRF can generate CPU interrupt requests.
0 = MODF and OVRF cannot generate CPU interrupt requests.
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte in the
receive data register before the next full byte enters the shift register. In an
overflow condition, the byte already in the receive data register is unaffected,
and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the receive data
register. Reset clears the OVRF bit.
1 = Overflow
0 = No overflow
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes high during
a transmission with the MODFEN bit set. In a master SPI, the MODF flag is set
if the SS pin goes low at any time with the MODFEN bit set. Clear the MODF bit
by reading the SPI status and control register (SPSCR) with MODF set and then
writing to the SPI control register (SPCR). Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data register
transfers a byte into the shift register. SPTE generates an SPTE CPU interrupt
request or an SPTE DMA service request if the SPTIE bit in the SPI control
register is set also.
NOTE:
Do not write to the SPI data register unless the SPTE bit is high.
For an idle master of idle slave that has no data loaded into its transmit buffer,
the SPTE will be set again within two bus cycles since the transmit buffer
empties into the shift register. This allows the user to queue up a 16-bit value to
send. For an already active slave, the load of the shift register cannot occur until
Data Sheet
230
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Serial Peripheral Interface Module (SPI)
MOTOROLA
FREESCALE [ Freescale ]
