Serial Communications Interface Module (SCI)
13.3.3.4 Framing Errors
If the data recovery logic does not detect a 1 where the stop bit should be in an
incoming character, it sets the framing error bit, FE, in SCS1. The FE flag is set at
the same time that the SCRF bit is set. A break character that has no stop bit also
sets the FE bit.
13.3.3.5 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other receivers in
multiple-receiver systems, the receiver can be put into a standby state. Setting the
receiver wakeup bit, RWU, in SCC2 puts the receiver into a standby state during
which receiver interrupts are disabled.
Depending on the state of the WAKE bit in SCC1, either of two conditions on the
PTF4/RxD pin can bring the receiver out of the standby state:
•
Address mark — An address mark is a 1 in the most significant bit position
of a received character. When the WAKE bit is set, an address mark wakes
the receiver from the standby state by clearing the RWU bit. The address
mark also sets the SCI receiver full bit, SCRF. Software can then compare
the character containing the address mark to the user-defined address of
the receiver. If they are the same, the receiver remains awake and
processes the characters that follow. If they are not the same, software can
set the RWU bit and put the receiver back into the standby state.
•
Idle input line condition — When the WAKE bit is clear, an idle character on
the PTF4/RxD pin wakes the receiver from the standby state by clearing the
RWU bit. The idle character that wakes the receiver does not set the
receiver idle bit, IDLE, or the SCI receiver full bit, SCRF. The idle line type
bit, ILTY, determines whether the receiver begins counting 1s as idle
character bits after the start bit or after the stop bit.
NOTE:
Clearing the WAKE bit after the PTF4/RxD pin has been idle can cause the receiver
to wake up immediately.
13.3.3.6 Receiver Interrupts
These sources can generate CPU interrupt requests from the SCI receiver:
•
•
SCI receiver full (SCRF) — The SCRF bit in SCS1 indicates that the receive
shift register has transferred a character to the SCDR. SCRF can generate
a receiver CPU interrupt request. Setting the SCI receive interrupt enable
bit, SCRIE, in SCC2 enables the SCRF bit to generate receiver CPU
interrupts.
Idle input (IDLE) — The IDLE bit in SCS1 indicates that 10 or 11 consecutive
1s shifted in from the PTF4/RxD pin. The idle line interrupt enable bit, ILIE,
in SCC2 enables the IDLE bit to generate CPU interrupt requests.
Data Sheet
180
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Serial Communications Interface Module (SCI)
MOTOROLA
FREESCALE [ Freescale ]
