Serial Communications Interface Module (SCI)
Functional Description
The SCI recognizes a break character when a start bit is followed by eight or nine
logic 0 data bits and a logic 0 where the stop bit should be.
Receiving a break character has these effects on SCI registers:
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Sets the framing error bit (FE) in SCS1
Sets the SCI receiver full bit (SCRF) in SCS1
Clears the SCI data register (SCDR)
Clears the R8 bit in SCC3
Sets the break flag bit (BKF) in SCS2
May set the overrun (OR), noise flag (NF), parity error (PE), or
reception-in-progress flag (RPF) bits
13.3.2.4 Idle Characters
An idle character contains all 1s and has no start, stop, or parity bit. Idle character
length depends on the M bit in SCC1. The preamble is a synchronizing idle
character that begins every transmission.
If the TE bit is cleared during a transmission, the PTF5/TxD pin becomes idle after
completion of the transmission in progress. Clearing and then setting the TE bit
during a transmission queues an idle character to be sent after the character
currently being transmitted.
NOTE:
When a break sequence is followed immediately by an idle character, this SCI
design exhibits a condition in which the break character length is reduced by one
half bit time. In this instance, the break sequence will consist of a valid start bit,
eight or nine data bits (as defined by the M bit in SCC1) of logic 0 and one half data
bit length of logic 0 in the stop bit position followed immediately by the idle
character. To ensure a break character of the proper length is transmitted, always
queue up a byte of data to be transmitted while the final break sequence is in
progress.
When queueing an idle character, return the TE bit to 1 before the stop bit of the
current character shifts out to the PTF5/TxD pin. Setting TE after the stop bit
appears on PTF5/TxD causes data previously written to the SCDR to be lost.
A good time to toggle the TE bit is when the SCTE bit becomes set and just before
writing the next byte to the SCDR.
13.3.2.5 Inversion of Transmitted Output
The transmit inversion bit (TXINV) in SCI control register 1 (SCC1) reverses the
polarity of transmitted data. All transmitted values, including idle, break, start,
and stop bits, are inverted when TXINV is at 1. See 13.7.1 SCI Control Register 1.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Serial Communications Interface Module (SCI)
Data Sheet
175
FREESCALE [ Freescale ]
