Serial Communications Interface Module (SCI)
13.3.2.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of the M bit
in SCI control register 1 (SCC1) determines character length. When transmitting
9-bit data, bit T8 in SCI control register 3 (SCC3) is the ninth bit (bit 8).
13.3.2.2 Character Transmission
During an SCI transmission, the transmit shift register shifts a character out to the
PTF5/TxD pin. The SCI data register (SCDR) is the write-only buffer between the
internal data bus and the transmit shift register. To initiate an SCI transmission:
1. Enable the SCI by writing a 1 to the enable SCI bit (ENSCI) in SCI control
register 1 (SCC1).
2. Enable the transmitter by writing a 1 to the transmitter enable bit (TE) in SCI
control register 2 (SCC2).
3. Clear the SCI transmitter empty bit by first reading SCI status register 1
(SCS1) and then writing to the SCDR.
4. Repeat step 3 for each subsequent transmission.
At the start of a transmission, transmitter control logic automatically loads the
transmit shift register with a preamble of 1s. After the preamble shifts out, control
logic transfers the SCDR data into the transmit shift register. A 0 start bit
automatically goes into the least significant bit (LSB) position of the transmit shift
register. A 1 stop bit goes into the most significant bit (MSB) position.
The SCI transmitter empty bit, SCTE, in SCS1 becomes set when the SCDR
transfers a byte to the transmit shift register. The SCTE bit indicates that the SCDR
can accept new data from the internal data bus. If the SCI transmit interrupt enable
bit, SCTIE, in SCC2 is also set, the SCTE bit generates a transmitter CPU interrupt
request.
When the transmit shift register is not transmitting a character, the PTF5/TxD pin
goes to the idle condition, logic 1. If at any time software clears the ENSCI bit in
SCI control register 1 (SCC1), the transmitter and receiver relinquish control of the
port E pins.
13.3.2.3 Break Characters
Writing a 1 to the send break bit, SBK, in SCC2 loads the transmit shift register with
a break character. A break character contains all 0s and has no start, stop, or parity
bit. Break character length depends on the M bit in SCC1. As long as SBK is at 1,
transmitter logic continuously loads break characters into the transmit shift register.
After software clears the SBK bit, the shift register finishes transmitting the last
break character and then transmits at least one logic 1. The automatic logic 1 at
the end of a break character guarantees the recognition of the start bit of the next
character.
Data Sheet
174
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
Serial Communications Interface Module (SCI)
MOTOROLA
FREESCALE [ Freescale ]
