Pulse-Width Modulator for Motor Control (PWMMC)
PWM Generators
For ease of software, the LDFQx bits are buffered. When the LDFQx bits are
changed, the reload frequency will not change until the previous reload cycle is
completed. See Figure 12-6.
NOTE:
When reading the LDFQx bits, the value is the buffered value (for example, not
necessarily the value being acted upon).
RELOAD
RELOAD
RELOAD
RELOAD RELOADRELOADRELOAD
CHANGE RELOAD
FREQUENCY TO
EVERY 4 CYCLES
CHANGE RELOAD
FREQUENCY TO
EVERY CYCLE
Figure 12-6. Reload Frequency Change
PWMINT enables CPU interrupt requests as shown in Figure 12-7. When this bit
is set, CPU interrupt requests are generated when the PWMF bit is set. When the
PWMINT bit is clear, PWM interrupt requests are inhibited. PWM reloads will still
occur at the reload rate, but no interrupt requests will be generated.
READ PWMF AS 1,
WRITE PWMF AS 0
OR
VDD
RESET
RESET
PWMF
CPU INTERRUPT
REQUEST
D
LATCH
PWM RELOAD
PWMINT
CK
Figure 12-7. PWM Interrupt Requests
To prevent a partial reload of PWM parameters from occurring while the software
is still calculating them, an interlock bit controlled from software is provided. This
bit informs the PWM module that all the PWM parameters have been calculated,
and it is “okay” to use them. A new modulus, prescaler, and/or PWM value cannot
be loaded into the PWM module until the LDOK bit in PWM control register 1 is set.
When the LDOK bit is set, these new values are loaded into a second set of
registers and used by the PWM generator at the beginning of the next PWM reload
cycle as shown in Figure 12-8, Figure 12-9, Figure 12-10, and Figure 12-11. After
these values are loaded, the LDOK bit is cleared.
NOTE:
When the PWM module is enabled (via the PWMEN bit), a load will occur if the
LDOK bit is set. Even if it is not set, an interrupt will occur if the PWMINT bit is set.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Pulse-Width Modulator for Motor Control (PWMMC)
Data Sheet
135
FREESCALE [ Freescale ]
