Central Processor Unit (CPU)
Opcode Map
Table 7-1. Instruction Set Summary (Sheet 7 of 7)
Effect
Source
Form
on CCR
Operation
Description
V H I N Z C
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SWI
Software Interrupt
–
–
1
–
–
– INH
83
9
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
TAP
TAX
TPA
Transfer A to CCR
Transfer A to X
CCR ← (A)
X ← (A)
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ
–
–
ꢀ INH
– INH
– INH
84
97
85
2
1
1
Transfer CCR to A
A ← (CCR)
TST opr
TSTA
DIR
INH
3D dd
4D
3
1
1
3
2
4
TSTX
INH
5D
Test for Negative or Zero
(A) – $00 or (X) – $00 or (M) – $00
0
–
–
ꢀ
ꢀ
–
TST opr,X
TST ,X
TST opr,SP
IX1
6D ff
7D
9E6D ff
IX
SP1
TSX
TXA
TXS
Transfer SP to H:X
Transfer X to A
H:X ← (SP) + 1
A ← (X)
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
– INH
– INH
– INH
95
9F
94
2
1
2
Transfer H:X to SP
(SP) ← (H:X) – 1
A
C
CCR
dd
dd rr
DD
DIR
DIX+
ee ff
EXT
ff
H
H
hh ll
I
ii
Accumulator
Carry/borrow bit
Condition code register
Direct address of operand
Direct address of operand and relative offset of branch instruction
Direct to direct addressing mode
n
Any bit
opr Operand (one or two bytes)
PC Program counter
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
Direct addressing mode
rel
rr
Relative program counter offset byte
Relative program counter offset byte
Direct to indexed with post increment addressing mode
High and low bytes of offset in indexed, 16-bit offset addressing
Extended addressing mode
Offset byte in indexed, 8-bit offset addressing
Half-carry bit
Index register high byte
High and low bytes of operand address in extended addressing
Interrupt mask
SP1 Stack pointer, 8-bit offset addressing mode
SP2 Stack pointer 16-bit offset addressing mode
SP Stack pointer
U
V
X
Z
&
|
Undefined
Overflow bit
Index register low byte
Zero bit
Logical AND
Logical OR
Immediate operand byte
Immediate source to direct destination addressing mode
IMD
IMM
INH
IX
Immediate addressing mode
Inherent addressing mode
Indexed, no offset addressing mode
Indexed, no offset, post increment addressing mode
Logical EXCLUSIVE OR
Contents of
–( ) Negation (two’s complement)
( )
IX+
#
Immediate value
IX+D
IX1
IX1+
IX2
M
Indexed with post increment to direct addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 8-bit offset, post increment addressing mode
Indexed, 16-bit offset addressing mode
Memory location
«
←
?
:
ꢀ
Sign extend
Loaded with
If
Concatenated with
Set or cleared
Not affected
N
Negative bit
—
7.8 Opcode Map
See Table 7-2.
MC68HC908MR32 • MC68HC908MR16 — Rev. 6.0
MOTOROLA Central Processor Unit (CPU)
Data Sheet
99
FREESCALE [ Freescale ]
