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MC908AP32CFAE 参数 Datasheet PDF下载

MC908AP32CFAE图片预览
型号: MC908AP32CFAE
PDF下载: 下载PDF文件 查看货源
内容描述: [MC908AP32CFAE]
分类和应用:
文件页数/大小: 325 页 / 4102 K
品牌: FREESCALE [ Freescale ]
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IRQ Registers  
IMASK1 — IRQ1 Interrupt Mask Bit  
Writing a logic 1 to this read/write bit disables IRQ1 interrupt requests. Reset clears IMASK1.  
1 = IRQ1 interrupt requests disabled  
0 = IRQ1 interrupt requests enabled  
MODE1 — IRQ1 Edge/Level Select Bit  
This read/write bit controls the triggering sensitivity of the IRQ1 pin. Reset clears MODE1.  
1 = IRQ1 interrupt requests on falling edges and low levels  
0 = IRQ1 interrupt requests on falling edges only  
17.6.2 IRQ2 Status and Control Register  
The IRQ2 status and control register (INTSCR2) controls and monitors operation of IRQ2. The INTSCR2  
has the following functions:  
Enables/disables the internal pullup device on IRQ2 pin  
Shows the state of the IRQ2 flag  
Clears the IRQ2 latch  
Masks IRQ2 interrupt request  
Controls triggering sensitivity of the IRQ2 interrupt pin  
Address:  
$001C  
Bit 7  
0
6
PUC0ENB  
0
5
0
4
0
3
2
0
1
IMASK2  
0
Bit 0  
MODE2  
0
Read:  
Write:  
Reset:  
IRQ2F  
ACK2  
0
0
0
0
0
= Unimplemented  
Figure 17-5. IRQ2 Status and Control Register (INTSCR2)  
PUC0ENB — IRQ2 Pin Pullup Enable Bit.  
Setting this bit to logic 1 disables the pullup on PTC0/IRQ2 pin.  
Reset clears this bit.  
1 = IRQ2 pin internal pullup is disabled  
0 = IRQ2 pin internal pullup is enabled  
IRQ2F — IRQ2 Flag Bit  
This read-only status bit is high when the IRQ2 interrupt is pending.  
1 = IRQ2 interrupt pending  
0 = IRQ2 interrupt not pending  
ACK2 — IRQ2 Interrupt Request Acknowledge Bit  
Writing a logic 1 to this write-only bit clears the IRQ2 latch. ACK2 always reads as logic 0. Reset clears  
ACK2.  
IMASK2 — IRQ2 Interrupt Mask Bit  
Writing a logic 1 to this read/write bit disables IRQ2 interrupt requests. Reset clears IMASK2.  
1 = IRQ2 interrupt requests disabled  
0 = IRQ2 interrupt requests enabled  
MODE2 — IRQ2 Edge/Level Select Bit  
This read/write bit controls the triggering sensitivity of the IRQ2 pin. Reset clears MODE2.  
1 = IRQ2 interrupt requests on falling edges and low levels  
0 = IRQ2 interrupt requests on falling edges only  
MC68HC908AP Family Data Sheet, Rev. 4  
Freescale Semiconductor  
275  
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