External Interrupt (IRQ)
•
Software clear — Software can clear an interrupt latch by writing to the appropriate acknowledge
bit in the interrupt status and control register (INTSCR). Writing a logic 1 to the ACK bit clears the
IRQ latch.
•
Reset — A reset automatically clears the interrupt latch.
The external interrupt pin is falling-edge-triggered and is software-configurable to be either falling-edge
or falling-edge and low-level-triggered. The MODE bit in the INTSCR controls the triggering sensitivity of
the IRQ pin.
When an interrupt pin is edge-triggered only, the interrupt remains set until a vector fetch, software clear,
or reset occurs.
When an interrupt pin is both falling-edge and low-level-triggered, the interrupt remains set until both of
the following occur:
•
•
Vector fetch or software clear
Return of the interrupt pin to logic 1
The vector fetch or software clear may occur before or after the interrupt pin returns to logic 1. As long as
the pin is low, the interrupt request remains pending. A reset will clear the latch and the MODE1 control
bit, thereby clearing the interrupt even if the pin stays low.
When set, the IMASK bit in the INTSCR mask all external interrupt requests. A latched interrupt request
is not presented to the interrupt priority logic unless the IMASK bit is clear.
NOTE
The interrupt mask (I) in the condition code register (CCR) masks all
interrupt requests, including external interrupt requests.
RESET
ACK1
TO CPU FOR
BIL/BIH
INSTRUCTIONS
VECTOR
FETCH
DECODER
VDD
V
INTERNAL
PULLUP
DEVICE
DD
IRQ1F
CLR
D
Q
IRQ1
INTERRUPT
REQUEST
SYNCHRONIZER
CK
IRQ1
IMASK1
MODE1
TO MODE
SELECT
LOGIC
HIGH
VOLTAGE
DETECT
Figure 17-2. IRQ1 Block Diagram
MC68HC908AP Family Data Sheet, Rev. 4
272
Freescale Semiconductor
FREESCALE [ Freescale ]
