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MC908AP32CFAE 参数 Datasheet PDF下载

MC908AP32CFAE图片预览
型号: MC908AP32CFAE
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内容描述: [MC908AP32CFAE]
分类和应用:
文件页数/大小: 325 页 / 4102 K
品牌: FREESCALE [ Freescale ]
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External Interrupt (IRQ)  
NOTE  
When using the level-sensitive interrupt trigger, avoid false interrupts by  
masking interrupt requests in the interrupt routine.  
The IRQ1 pin has a permanent internal pullup device connected, while the IRQ2 pin has an optional  
pullup device that can be enabled or disabled by the PUC0ENB bit in the INTSCR2 register.  
17.5 IRQ Module During Break Interrupts  
The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear the latch during  
the break state. (See Chapter 21 Break Module (BRK).)  
To allow software to clear the IRQ latch during a break interrupt, write a logic 1 to the BCFE bit. If a latch  
is cleared during the break state, it remains cleared when the MCU exits the break state.  
To protect CPU interrupt flags during the break state, write a logic 0 to the BCFE bit. With BCFE at logic  
0 (its default state), writing to the ACK bit in the IRQ status and control register during the break state has  
no effect on the IRQ interrupt flags.  
17.6 IRQ Registers  
Each IRQ is controlled and monitored by an status and control register.  
IRQ1 Status and Control Register — $001E  
IRQ2 Status and Control Register — $001C  
17.6.1 IRQ1 Status and Control Register  
The IRQ1 status and control register (INTSCR1) controls and monitors operation of IRQ1. The INTSCR1  
has the following functions:  
Shows the state of the IRQ1 flag  
Clears the IRQ1 latch  
Masks IRQ1 interrupt request  
Controls triggering sensitivity of the IRQ1 interrupt pin  
Address:  
$001E  
Bit 7  
0
6
0
5
0
4
0
3
2
0
1
IMASK1  
0
Bit 0  
MODE1  
0
Read:  
Write:  
Reset:  
IRQ1F  
ACK1  
0
0
0
0
0
0
= Unimplemented  
Figure 17-4. IRQ1 Status and Control Register (INTSCR1)  
IRQ1F — IRQ1 Flag Bit  
This read-only status bit is high when the IRQ1 interrupt is pending.  
1 = IRQ1 interrupt pending  
0 = IRQ1 interrupt not pending  
ACK1 — IRQ1 Interrupt Request Acknowledge Bit  
Writing a logic 1 to this write-only bit clears the IRQ1 latch. ACK1 always reads as logic 0. Reset clears  
ACK1.  
MC68HC908AP Family Data Sheet, Rev. 4  
274  
Freescale Semiconductor  
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