Input/Output (I/O) Ports
SDA and SCL — Multi-Master IIC Data and Clock
The SDA and SCL pins are multi-master IIC data and clock pins. Setting the MMEN bit in the MMIIC
control register 1 (MMCR1) configures the PTB0/SDA and PTB1/SCL pins for MMIIC function and
overrides any control from the port I/O logic.
TxD and RxD — SCI Transmit and Receive Data
The TxD and RxD pins are SCI transmit and receive data pins. Setting the ENSCI bit in the SCI control
register 1 (SCC1) configures the PTB2/TxD and PTB3/RxD pins for SCI function and overrides any
control from the port I/O logic.
T1CH0 and T1CH1 — Timer 1 Channel I/O
The T1CH0 and T1CH1 pins are the TIM1 input capture/output compare pins. The edge/level select
bits, ELSxB:ELSxA, determine whether the PTB4/T1CH0–PTB5/T1CH1 pins are timer channel I/O
pins or general-purpose I/O pins.
T2CH0 and T2CH1 — Timer 2 Channel I/O
The T2CH0 and T2CH1 pins are the TIM2 input capture/output compare pins. The edge/level select
bits, ELSxB:ELSxA, determine whether the PTB6/T2CH0–PTB7/T2CH1 pins are timer channel I/O
pins or general-purpose I/O pins.
16.3.2 Data Direction Register B (DDRB)
Data direction register B determines whether each port B pin is an input or an output. Writing a logic 1 to
a DDRB bit enables the output buffer for the corresponding port B pin; a logic 0 disables the output buffer.
Address:
$0005
Bit 7
6
DDRB6
0
5
DDRB5
0
4
DDRB4
0
3
DDRB3
0
2
DDRB2
0
1
DDRB1
0
Bit 0
DDRB0
0
Read:
Write:
Reset:
DDRB7
0
Figure 16-7. Data Direction Register B (DDRB)
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears DDRB[7:0], configuring all port B pins
as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1.
Figure 16-8 shows the port B I/O logic.
MC68HC908AP Family Data Sheet, Rev. 4
264
Freescale Semiconductor
FREESCALE [ Freescale ]
