Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port B
7.4.3 Port B Logic
Figure 7-6 shows the port B I/O logic.
V
DD
PBPU7
FROM MOR1
READ $0005
WRITE $0005
RESET
DATA DIRECTION
REGISTER B
BIT DDRB7
PORT B DATA
REGISTER
BIT PB7
WRITE $0001
READ $0001
PB7
IRQ
FROM OPTION
REGISTER
V
DD
EXTERNAL
INTERRUPT
REQUEST
D
IRQ
LATCH
Q
FROM OTHER
PORT B PINS
C
Q
R
I BIT
FROM CCR
IRQ
RESET
EXTERNAL INTERRUPT VECTOR FETCH
Figure 7-6. Port B I/O Logic
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Parallel Input/Output (I/O)
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