Freescale Semiconductor, Inc.
Parallel Input/Output (I/O)
Port A
7.3.2 Data Direction Register A
The contents of data direction register A (DDRA) shown in Figure 7-2
determine whether each port A pin is an input or an output. Writing a
logic 1 to a DDRA bit enables the output buffer for the associated port A
pin; a logic 0 disables the output buffer. A reset clears all DDRA bits,
configuring all port A pins as inputs.
Address: $0004
Bit 7
DDRA7
0
6
DDRA6
0
5
DDRA5
0
4
DDRA4
0
3
DDRA3
0
2
DDRA2
0
1
DDRA1
0
Bit 0
DDRA0
0
Read:
Write:
Reset:
Figure 7-2. Data Direction Register A (DDRA)
DDRA7–DDRA0 — Port A Data Direction Bits
These read/write bits control port A data direction. Reset clears bits
DDRA7–DDRA0.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE: Avoid glitches on port A pins by writing to the port A data register before
changing DDRA bits from logic 0 to logic 1.
MC68HC705C8A — Rev. 3
MOTOROLA
Technical Data
Parallel Input/Output (I/O)
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