Freescale Semiconductor, Inc.
Low-Power Modes
STOP
WAIT
OSCILLATOR ACTIVE
TIMER, SCI, AND SPI
CLOCKS ACTIVE
CPU CLOCKS STOPPED
CLEAR I BIT
STOP OSCILLATOR
AND ALL CLOCKS
CLEAR I BIT
NO
NO
RESET
YES
RESET
YES
EXTERNAL
INTERRUPT
(IRQ)
NO
EXTERNAL
INTERRUPT
(IRQ)
NO
YES
YES
INTERNAL TIMER
INTERRUPT
YES
NO
TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
RESTART CPU CLOCK
YES
INTERNAL SCI
INTERRUPT
NO
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. STACK
b. SET I BIT
c. VECTOR TO
INTERRUPT ROUTINE
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT:
a. STACK
NO
YES
INTERNAL SPI
INTERRUPT
b. SET I BIT
c. VECTOR TO
INTERRUPT ROUTINE
Figure 6-1. Stop/Wait Mode Function Flowchart
During stop mode, the I bit in the condition code register (CCR) is
cleared to enable external interrupts. All other registers and memory
remain unaltered. All input/output (I/O) lines remain unchanged. The
processor can be brought out of stop mode only by an external interrupt
or reset.
Technical Data
70
MC68HC705C8A — Rev. 3
Low-Power Modes
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